Fujitsu F2MC-16LX Hardware Manual page 698

INDEX
ODR
Port 4 Output Terminal Register (ODR4)
One-shot
One-shot Operation Modes.
One-to-one Mode
Baud Rate of the External Clock
(One-to-one Mode)
Operating Mode
.......................................... 176, 416
Operating Mode
Operating State
.......................................... 372
Check Operating State
Operation Mode
Counter Operation Mode
Operation in Synchronous Mode
(Operation Mode 2)
........................................ 373
Reload Operation Mode
........................................ 369
Selects Operation Mode
Operation Mode Control Register
PPG0/2/4 Operation Mode Control Register
(PPGC0/PPGC2/PPGC4)
PPG1/PPG3/PPG5 Operation Mode Control Register
(PPGC1/PPGC3/PPGC5)
Operation Modes
One-shot Operation Modes.
Operation State
Operation State of Serial I/O
Operation Status
Operation Status in Low-power Consumption
.................................................. 161
Mode
Operation Status in Standby Mode
Oscillation Clock
Oscillation Clock Frequency and Serial Clock Input
............................................590
Frequency
Oscillation Stabilization Wait Time
Oscillation Stabilization Wait Time
Oscillation Stabilization Wait Time Function
Oscillation Stabilization Wait Times
Reset Factors and Oscillation Stabilization Wait
.................................................. 116
Times
Oscillation Stabilization Waiting
Oscillation Stabilization Waiting Reset State
Oscillator
Connection of Oscillator and External Clock
OUT
........................................ 353
IN,OUT,SETUP Token
Output Compare
Block Diagram of Output Compare
List of Output Compare Registers
Output Compare Control Registers
Output Compare Control Registers
(OCS0 to OCS3)
Output Compare Registers
Output Compare Registers (OCCP0 to OCCP3)
Output Control Register
PPG0 to PPG5 Output Control Register
(PPG01/PPG23/PPG45)
682
.................. 202
................................... 373
................................. 503
......................................386
................................ 509
.........................408
.........................410
................................... 373
.................................. 470
.......................... 151
.................138, 173
............213
............. 117
............. 139
.........................248
........................... 247
.................................... 249
......... 248
.......................... 413
Output Waveform
Example of Output Waveform
P
Package Dimension
Package Dimension (LQFP-120)
Packet
....................................................... 342
Data Packet
............................................... 343
Handshake Packet
....................................... 340
Setting of Token Packet
Packet End
............................................. 348
Packet End Timing
Packet Transfer
.......................................... 304
Packet Transfer Mode
PACSR
Address Detection Control Register (PACSR)
PADR
Detect Address Setting Registers (PADR0,PADR1)
Patch Program
Operation of Address Match Detection Function
at Storing Patch Program in E
Pause-conversion
Operation of Pause-conversion Mode
PC
........................................... 39
Program Counter (PC)
PCB
Program Bank Register (PCB)<Initial Value: Value in Reset
................................................. 40
Vector>
PDR
Port Data Register (PDR0 to PDRB)
Peripheral Equipment
Condition of Peripheral Equipment Connected
............................................... 427
Outside
Physical Address
Relation between Access Area and Physical Address
......................................................... 179
Pin
Pin State in External Bus 16-bit Data Bus and Non-multiplex
16-bit External Bus Mode
Pin State in External Bus 8-bit Data Bus and Non-multiplex
8-bit External Bus Mode
Pin Assignment
Pin Assignment (LQFP-120)
Pin Function
........................................................ 11
Pin Function
Pins
State of Pins after Mode Data Read
PLL Clock
Selection of PLL Clock Multiplication Rate
PLL Clock Mode
Main Clock Mode, PLL Clock Mode,
Sub Clock Mode
Port 0
Port 0,1 Pull-up Resistance Register (RDR0,RDR1)
............................... 258
................................ 8
........... 551
... 553
2
........ 559
PROM
...................... 444
....................... 200
........................ 168
......................... 170
................................... 10
......................... 123
.............. 136
.................................... 135
... 202