Fujitsu F2MC-16LX Hardware Manual page 171

Cancellation of Timebase Timer Modes
The low-power consumption circuit cancels the timebase timer mode by generating a reset input or an
interrupt request.
Return by external reset
The external reset initializes the mode to the main clock mode.
Return by interrupt
If there is an interrupt request higher than level 7 from peripheral circuit and others in the timebase timer
mode (except for IL2, IL1, IL0 of the interrupt control register (ICR) = "111
consumption control circuit cancels the timebase timer mode. After cancellation of timebase timer modes,
the action is the same as for ordinary interrupt processing. When an interrupt is acceptable according to the
setting of the I flag of the condition code register (CCR), the interrupt level mask register (ILM), and the
interrupt control register (ICR), interrupt processing is performed. When an interrupt is not acceptable,
processing from the instruction succeeding the one before entering timebase timer mode continues.
Notes:
• When handling an interrupt, the CPU usually services the interrupt after executing the instruction
that follows the one specifying the timebase timer mode. When transition to timebase timer mode
and acceptance of an external bus hold request have occurred at the same time, interrupt
processing may transit before executing the next instruction.
• When using the USB, the transition to the timebase timer mode is disabled.
CHAPTER 6 LOW-POWER CONSUMPTION MODE
"), the low-power
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