Fujitsu F2MC-16LX Hardware Manual page 149

Note:
The machine clock selection bit (MCS) is initialized by reset to main clock selection.
Table 5.3-1 Functions of Clock Select Register (CKSCR) Bits (1/2)
Bit name
SCM:
bit 15 Sub clock
display bit
MCM:
bit 14 PLL clock
display bit
WS1, WS0:
Oscillation
bit 13
stabilization
bit 12
wait time
selection bits
SCS:
bit 11 Sub clock
selection bit
MCS:
bit 10 PLL clock
selection bit
• Bit indicating the main clock or sub clock, whichever selected as the machine clock.
• A "0" in this bit indicates that the sub clock has been selected. A "1" in the bit indicates that the
main or PLL clock has been selected.
• If SCS = 1 and SCM = 0, now is the main clock oscillation stabilization wait time.
• Bit indicating the main or PLL clock, whichever selected as the machine clock.
• A "0" in this bit indicates that the PLL clock has been selected. A "1" in the bit indicates that the
main or sub clock has been selected.
• If the PLL clock selection bit (MCS) = 0 and MCM = 1, now is the PLL clock oscillation
stabilization wait time.
• These bits are used to select an oscillation stabilization wait time required for the oscillation
clock when the stop mode is canceled, when transition occurs from sub clock mode to main
clock mode, or when transition occurs from sub clock mode to PLL clock.
• Initialized to "11
" by every reset cause.
B
Note:
The oscillation stabilization wait time must be set to a suitable value for the oscillator to use. See
"4.2 Reset Factors and Oscillation Stabilization Wait Times". Please set the setting of "00
at the main clock mode.
Reference:
The oscillation stabilization wait time for PLL clock is fixed to 2
• Bit for specifying main or sub clock as the machine clock.
• A "0" in this bit selects the sub clock. A "1" in the bit selects the main clock.
• If "1" is written to this bit when it is "0", the main clock oscillation stabilization wait time is
produced, thereby clearing the timebase timer automatically.
• When the sub clock is selected, it is used as the operating clock. (If the low-speed oscillation is
32 kHz, the machine clock is 8 kHz.)
• When both SCS and MCS are "0", SCS has priority and sub clock is selected.
• Initialized to "1" by every reset cause.
• Bit for selecting main or PLL clock as the machine clock.
• A "0" in this bit selects the PLL clock. A "1" in the bit selects the main clock.
• If "0" is written to this bit when it is "1", the PLL clock oscillation stabilization wait time is
produced, thereby clearing the timebase timer automatically. Also, the interrupt request flag bit
(TBOF) of the timebase timer control register (TBTC) is cleared.
• The PLL clock oscillation stabilization wait time is fixed to 2
is 6 MHz, the oscillation stabilization wait time will be approximately 2.73 ms.)
• If the main clock is selected, the operating clock frequency will be the oscillation clock
frequency-divided by 2. (If the oscillation clock is 6 MHz, the operating clock will be 3 MHz.)
• Initialized to "1" by every reset cause.
Note:
To write "0" if when MCS bit is "1", make sure that the timebase timer interrupt have been
masked using the TBTC register interrupt request enable bit (TBIE) or interrupt level mask
register (ILM).
Functions
14
/HCLK.
14
/HCLK. (If the oscillation clock
CHAPTER 5 CLOCK
" only
B
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