Fujitsu F2MC-16LX Hardware Manual page 136

CHAPTER 4 RESET
Mode Fetch
Once the reset is released, the CPU transfers the reset vector and mode data into the appropriate register in
the CPU core. The reset vector and mode data are assigned to the four bytes of FFFFDC
When the reset is released, the CPU immediately outputs these addresses to the bus before fetching the
reset vector and mode data. The CPU starts the mode fetch process at the address pointed to by the reset
vector.
Figure 4.4-2 shows how the reset vector and mode data are transferred.
FFFFDF
FFFFDE
FFFFDD
FFFFDC
Reference:
The object from which to read the reset vector and mode data (either internal ROM or external
memory) can be specified using the mode pins. It is recommended that the internal vector mode be
specified using the mode pins in single chip mode or internal ROM external bus mode. This is
because specifying the external vector mode with the mode pins causes an attempt to read the reset
vector and mode data from the external memory, instead of the internal memory.
Mode data (address: FFFFDF
The contents of the mode register can be modified only by reset operation. The mode register settings will
take effect after reset operation. Refer to the "7.3 Mode Data" section for details of the mode data.
Reset vector (address "FFFFDC
Write the execution start address after the completion of the reset operation. Execution begins from the
address of this content.
120
Figure 4.4-2 Reset Vector and Mode Data Transfers
Memory space
Mode data
H
Reset vector bit 23 to 16
H
Reset vector bit 15 to 8
H
Reset vector bit 7 to 0
H
)
H
to FFFFDE
H
2
F MC-16LX CPU core
Micro ROM
Reset sequence
")
H
to FFFFDF
H
Mode
register
PCB
PC
.
H