Fujitsu F2MC-16LX Hardware Manual page 258

CHAPTER 12 16-BIT I/O TIMER
Block Diagram of 16-bit Free-run Timer
Figure 12.2-5 shows the 16-bit free-run timer block diagram.
Compare Clear Register (CPCLR)
Figure 12.2-6 shows the bit configuration of the compare clear register (CPCLR).
Figure 12.2-6 Bit Configuration of Compare Clear Register (CPCLR)
15
CL15 CL14 CL13 CL12 CL11 CL10 CL09 CL08
00008B
H
R/W R/W
CL07 CL06 CL05 CL04 CL03 CL02 CL01 CL00
00008A
H
R/W R/W
The compare clear register (CPCLR) is a 16-bit length compare register that is compared with the 16-bit
free-run timer. Since the CPCLR register has an indefinite, initial value, you must set the value before
enabling the operation. Moreover, please access the CPCLR register the word.
When the MODE bit of the timer control status register (TCCS) is set to "1", 16-bit free-run timer value is
cleared to "0000
register value is matched with 16-bit free-run timer value, 16-bit free-run timer value is initialized to
"0000 ", and the compare clear interrupt flag is set. When the interrupt is enabled on the compare clear
H
interrupt flag = "1", the interrupt request is generated to CPU.
242
Figure 12.2-5 Block Diagram of 16-bit Free-run Timer
IVF IVFE STOP MODE CLR CLK2 CLK1
16-bit free-run timer
16-bit compare clear register
Compare
MSI 2 to MSI 0
circuit
14 13 12
R/W R/W R/W
7 6 5 4
R/W R/W R/W
" at matching between the register value and 16-bit free-run timer value. And when the
H
Interrupt request #36
Count value output T15 to T00
ICLR ICRE
11 10 9 8
R/W R/W R/W
3 2 1 0
R/W R/W R/W
φ
Comparator
CLK0
Clock
Interrupt request #36
CPCLR
Compare clear register upper
XXXXXXXX
Initial value
CPCLR
Compare clear register lower
Initial value XXXXXXXX
B
B