Fujitsu F2MC-16LX Hardware Manual page 264

CHAPTER 12 16-BIT I/O TIMER
Block Diagram of Output Compare
Figure 12.2-10 shows the output compare block diagram.
Output Compare Registers (OCCP0 to OCCP3)
Figure 12.2-11 shows the bit configurations of the output compare registers (OCCP0 to OCCP3).
Figure 12.2-11 Bit Configurations of Output Compare Registers (OCCP0 to OCCP3)
ch0:007919
H
ch1:00791B
H
ch2:00791D
H
ch3:00791F
H
ch0:007918
H
ch1:00791A
H
ch2:00791C
H
ch3:00791E
H
The output compare registers (OCCP0 to OCCP3) are 16-bit length compare registers any of which is
compared with the 16-bit free-run timer. Since the registers have indefinite, initial values, set the initial
values before enabling them. Please access the OCCP0 to OCCP3 register the word. When the values of the
OCCP0 to OCCP3 registers match that of the 16-bit free-run timer, the compare signal is generated and the
output compare interrupt flag is set. In addition, if output is enabled, the output level corresponding to each
of the compare registers is reversed.
248
Figure 12.2-10 Block Diagram of Output Compare
Compare control
Compare register 0,2
16-bit timer counter value (T15 to T00)
Compare control
Compare register 1,3
ICP1 ICP0 ICE1 ICE0
Control unit
Each
control blocks
15 14 13
C15 C14 C13 C12
R/W R/W R/W R/W R/W
7 6 5
C07 C06 C05 C04
R/W R/W R/W R/W R/W
TQ
CMOD
TQ
12 11 10 9
C11 C10 C09
R/W R/W
4 3 2 1
C03 C02 C01
R/W R/W
OUT0,OUT2
OTE0
OTE1
OUT1,OUT3
Compare 1, 3 interrupt #29,#31
Compare 0, 2 interrupt #29,#31
OCCP0 to OCCP3
8
Output compare register upper
C08
Initial value XXXXXXXX
R/W
OCCP0 to OCCP3
0
Output compare register lower
C00
Initial value XXXXXXXX
R/W
B
B