Fujitsu F2MC-16LX Hardware Manual page 487

Figure 20.3-1 Transition Diagram of Operation in Extended I/O Serial Interface
Stop state (Transfer complete)
STRT=0, BUSY=0
MODE=0
MODE=0
STOP=0
&
& STOP=0
STRT=1
&
END
Transfer operation
STRT=1, BUSY=1
Figure 20.3-2 Conceptual Diagram of Reading/writing Serial Data Register
Data bus
SOT
Read
SIN
Write
Interrupt output
Extended I/O
serial interface
(1) When MODE=1, transfer is terminated by the shift clock counter.This allows SIR=1 to go into read/
write state. If the SIE bit is "1", the interruption signal is generated. However, when SIE is inactive, or
when writing "1" in STOP causes the suspend of transfer, interrupt signals are not generated.
(2) Once the serial data register is read or written, interrupt requests are cleared, and serial transfer starts.
CHAPTER 20 EXTENDED I/O SERIAL INTERFACE
STOP=0 & STRT=0
STOP=1
STOP=1
STOP=0
&
STRT=1
MODE=1 & END & STOP=1
SDR R/W & MODE=1
Data bus
Read
Write
(1)
Interrupt input
(2)
Data bus
Reset
STOP
STRT=0, BUSY=0
STOP=1
Serial data register R/wait
STRT=1, BUSY=0
MODE=1
CPU
Interrupt
controller
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