Fujitsu F2MC-16LX Hardware Manual page 568

CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION
Table 24.3-1 Functions of Address Detection Control Register (PACSR)
Bit Name
bit 0 Reserved bit
bit 1 AD0E:
Address match
detection enable bit 0
bit 2 Reserved bit
bit 3 AD1E:
Address match
detection enable bit 1
bit 4 to Reserved bit
bit 7
552
Always set to "0".
The address match detection operation with the detect address setting
register 0 (PADR0) is enabled or disabled.
When set to "0": Disables the address match detection operation.
When set to "1": Enables the address match detection operation.
• When the value of detect address setting register 0 (PADR0) matches
with the value of address latch at enabling the address match detect
operation (AD0E = 1), the INT9 instruction is immediately executed.
Always set to "0".
The address match detection operation with the detect address setting
register 1 (PADR1) is enabled or disabled.
When set to "0": Disables the address match detection operation.
When set to "1": Enables the address match detection operation.
• When the value of detect address setting registers 1 (PADR1) matches
with the value of address latch at enabling the address match detection
operation (AD1E = 1), the INT9 instruction is immediately executed.
Always set to "0".
Function