Fujitsu F2MC-16LX Hardware Manual page 131

External reset
An external reset is generated by inputting the "L" level signal to external reset pin (RST). The input time
of the "L" level signal to the (RST) pin must be continued for 16 machine cycles (16/φ) or more.
The external reset, that is, the RST pin input reset does not produce the oscillation stabilization wait time.
Reference:
Only when a reset request via the RST pin is generated, a reset cause generated in write operation
(An example of such write operation is the MOV instruction which is issued during execution of a
transfer instruction.) causes a wait state for release of the reset after completion of the instruction.
Thus, the write process terminates normally even if a reset signal is input during write operation.
However, if a string instruction such as MOVS is used, transfer of all the data will not be guaranteed.
This is because the instruction accepts a reset before the transfer data for the specified counter
value is completed. A reset is accepted also if extension of the bus cycle via the RDY pin continues
for 16 machine cycles or more during access to the external bus.
Software reset
Software reset causes an internal reset by writing "0" to the internal reset signal generation bit (RST) of the
low-power consumption mode control register (LPMCR). Software reset does not cause the oscillation
stabilization wait time.
Reference:
Clock definition
HCLK: Oscillation clock, which is provided via the high speed oscillation pin.
MCLK: Main clock (HCLK frequency divided by 4)
SCLK: Sub clock (a clock which is frequency divided by 4 on the clock provided via the low speed
oscillation pin)
φ: Machine clock (CPU operation clock)
1/φ: machine cycle (CPU operating clock cycle)
Refer to the "5.1 Outline of Clock" section for details of the machine clocks.
Note:
A reset generated in stop or sub clock mode produces an 2
(approximately 21.85 ms at the oscillation clock is 6 MHz).
Refer to the "5.4 Clock Mode" section for details of the clock mode.
CHAPTER 4 RESET
17
/HCLK oscillation stabilization wait time
115