Fujitsu F2MC-16LX Hardware Manual page 689

A
A
.................................................. 34
Accumulator (A)
A/D Control Status Register
A/D Control Status Register (High) (ADCS1)
A/D Control Status Register (Low) (ADCS0)
A/D Conversion Channel Set Register
A/D Conversion Channel Set Register (ADMR)
A/D Converter
Block Diagram of 8/10-bit A/D Converter
Function of 8/10-bit A/D Converter
Precautions when Using 8/10-bit A/D Converter
Register List of 8/10-bit A/D Converter
A/D Data Register
A/D Data Register (ADCR1/ADCR0)
A/D-converted Data
A/D-converted Data Protection Function
Access Mode
..................................................... 176
Access Mode
Accumulator
.................................................. 34
Accumulator (A)
Acknowledge
..................................................... 537
Acknowledge
ADCR
A/D Data Register (ADCR1/ADCR0)
ADCS
A/D Control Status Register (High) (ADCS1)
A/D Control Status Register (Low) (ADCS0)
Address Detection Control Register
Address Detection Control Register (PACSR)
Address Generation
Address Generation Type
Address Match Detection Function
Block Diagram of Address Match Detection
.............................................. 549
Function
List of Registers and Reset Values of Address Match
Detection Function
Operation of Address Match Detection Function
Operation of Address Match Detection Function
at Storing Patch Program in E
Overview of Address Match Detection Function
Program Example for Address Match Detection
.............................................. 561
Function
Addressing
................................................ 536, 616
Addressing
............................................... 618
Direct Addressing
............................................. 623
Indirect Addressing
Addressing Type
Addressing Types by Bank
ADER
Analog Input Enable Register (ADER0,ADER1)
ADMR
A/D Conversion Channel Set Register (ADMR)
Analog Input Enable Register
Analog Input Enable Register (ADER0,ADER1)
........... 434
............ 436
........ 438
................ 431
........................ 430
........ 448
................... 433
..................... 440
.................. 446
..................... 440
........... 434
............ 436
........... 551
....................................... 28
................................. 550
........ 555
2
........ 559
PROM
........ 548
..................................... 29
....... 203
........ 438
....... 203
Arbitration
.........................................................536
Arbitration
ARSR
Automatic Ready Function Selection Register
................................................184
(ARSR)
Asynchronous Mode
Operation in Asynchronous Mode
Automatic Algorithm
Automatic Algorithm End Timing
Automatic Ready Function Selection Register
Automatic Ready Function Selection Register
................................................184
(ARSR)
Automatic Transfer
Data Number Automatic Transfer Mode
B
Bank
Addressing Types by Bank
Bank Select Prefix
.................................................43
Bank Select Prefix
BAP
Buffer address Pointer (BAP)
Basic Component
The Serial on Board Writing Basic Component
Baud Rate
Baud Rate of the External Clock
(One-to-one Mode)
Baud Rate of the External Clock Using the Dedicated
Baud Rate Generator
Baud Rate of the Internal Clock Using the Dedicated
Baud Rate Generator
UART Baud Rate Selection
Bidirectional Communication
Bidirectional Communication Function
Bit
Priority Level of STP,SLP,and TMD Bit
Block Diagram
...........................................182, 239
Block Diagram
Block Diagram in Extended I/O Serial Interface
Block Diagram of 16-bit Free-run Timer
Block Diagram of 16-bit Reload Timer
Block Diagram of 8/10-bit A/D Converter
Block Diagram of 8/16-bit PPG Timer
Block Diagram of Address Match Detection
...............................................549
Function
Block Diagram of Clock Generation Section
Block Diagram of Delayed Interrupt Generation
................................................110
Module
Block Diagram of DTP/External Interrupt
Block Diagram of External Reset Pin
Block Diagram of Input Capture
Block Diagram of Low-power Consumption Control
.................................................145
Circuit
Block Diagram of Output Compare
Block Diagram of PWC Timer
Block Diagram of ROM Mirror Function Select
................................................544
Module
Block Diagram of the MB90330 Series
INDEX
...........................506
...........................568
...................305
......................................29
...................................80
..........588
.................................503
...............................502
...............................501
...................................500
....................512
...................149
.........460
...................242
.....................387
.................431
.....................405
..............129
.................422
.......................118
.............................252
.........................248
...............................357
........................7
673