Transmit Interrupt Generation And Flag Set Timing - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 21 UART
21.5.2

Transmit Interrupt Generation and Flag Set Timing

An interrupt during transmission is generated when serial output data register 0 to 3
(SODR0 to SODR3) becomes empty, or ready to accommodate the next data to transmit.
Transmit Interrupt Generation and Flag Set Timing
The sending data empty flag bit (SSR0 to SSR3: TDRE) is set to "1" in the state that the sending data that is
written to the serial output data registers 0 to 3 (SODR0 to SODR3) is transferred to the sending shift
register, the subsequent data goes into the readable state. When the subsequent data is written to the serial
output data registers 0 to 3 (SODR0 to SODR3), the sending data empty flag bit (SSR0 to SSR3: TDRE) is
cleared to "0".
Figure 21.5-2 shows the timing of sending operation and the set of flags.
[Operation mode 0, 1]
SODR0 to SODR3 write
TDRE
SOT0 to SOT3 output
[Operation mode 2]
SODR0 to SODR3 write
TDRE
SOT0 to SOT3 output
ST
D0 to D7 : Data bit
SP
A/D
498
Figure 21.5-2 Timing of Sending Operation and the Set of Flags
Transfer interrupt generation
ST D0 D1 D2 D3 D4
Transfer interrupt generation
D0 D1 D2 D3 D4
: Start bit
: Stop bit
: Address/Data selection bit
Transfer interrupt generation
SP
D5 D6 D7
SP
A/D
Transfer interrupt generation
D0 D1 D2 D3 D4
D5 D6 D7
ST D0 D1 D2 D3
D5 D6 D7