Ppg1/Ppg3/Ppg5 Operation Mode Control Register (Ppgc1/Ppgc3/Ppgc5) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 17 8/16-BIT PPG TIMER
17.2.2 PPG1/PPG3/PPG5 Operation Mode Control Register
(PPGC1/PPGC3/PPGC5)
Configuration and functions of PPG1/PPG3/PPG5 operation mode control register
(PPGC1/PPGC3/PPGC5) are described.

PPG1/PPG3/PPG5 Operation Mode Control Register (PPGC1/PPGC3/PPGC5)

The PPG1/PPG3/PPG5 operation mode control register (PPGC1/PPGC3/PPGC5) selects the operation
mode of ch1/ch3/ch5, controls the terminal output, selects the count clock, and controls the trigger.
Figure 17.2-3 shows the bit configuration of PPG1/PPG3/PPG5 operation mode control registers (PPGC1/
PPGC3/PPGC5).
Figure 17.2-3 Bit Configuration of PPG1/PPG3/PPG5 Operation Mode Control Registers
ch1 : 000047
H
ch3 : 000049
H
ch5 : 00004B
H
The following describes functions of each bit of PPG1/PPG3/PPG5 operation mode control registers
(PPGC1/PPGC3/PPGC5):
[bit 15] PEN1: ppg Enable (operation permission)
The operation start and operation mode of PPG1/PPG3/PPG5 are selected.
PEN1
0
1
• When this bit is set to "1", PPG count starts.
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
[bit 14] Undefinition bit
The lead value is irregular. Nothing is affected when it is written.
410
(PPGC1/PPGC3/PPGC5)
15 14 13 12
−
PEN1 PE10 PIE1 PUF1
( − )
(R/W) (R/W) (R/W) (R/W)
(0) (X) (0) (0)
Operation stop ("L" level power output maintenance)
PPG Enabling Operations
11 10 9 8
MD1 MD0
Reserved
(R/W) (R/W) (R/W)
(0) (0) (0) (1)
Operating State
PPGC1/PPGC3/PPGC5
PPG Operation mode control register
Read/Write
Initial value