Fujitsu F2MC-16LX Hardware Manual page 53

Zero flag (Z)
If the operation result is all 0, Z flag is set, and, besides, cleared.
Overflow flag (V)
The V flag is set and cleared when a signed numeric value overflow occurs and does not occur,
respectively, as a result of operation execution.
Carry flag (C)
The C flag is set and cleared when the MSB is carried up or down and is not occurred, respectively, as a
result of operation execution.
Register Bank Pointer (RP)
The register bank pointer (RP) indicates the relation between the F
the internal RAM address. The RP indicates the current start memory address of register bank in use by the
conversion expression, (00180
The RP consisting of 5-bit can take values from 00
The register bank can be allocated to the memory of 000180
general-purpose register even within this range if the register bank is not the internal RAM. The 8-bit
immediate value can be transferred to the RP on the instruction although only the lower 5 bits of those data
are actually used.
Figure 2.3-8 Configuration of Register Bank Pointer (RP)
Interrupt Level Mask Register (ILM)
The interrupt level mask register (ILM) consisting of 3-bit indicates the interrupt mask level of CPU. An
interrupt request is accepted only when its level is higher than the level indicated by these 3 bits. Level 0 is
the highest priority interrupt and level 7 is the lowest priority interrupt (see Table 2.3-1). Therefore, an
acceptable interrupt level value must be smaller than the current ILM value. When an interrupt is accepted,
the interrupt level value is set in the ILM and thereafter no interrupt is accepted when its priority is same or
lower than it. ILM is initialized to "0" by reset. The 8-bit immediate value can be transferred to the ILM
register on the instruction although only the lower 3-bit of those data are actually used.
Figure 2.3-9 shows the configuration of the interrupt level mask register while Table 2.3-1 shows the level
indicated by the interrupt level mask register (ILM).
+ RP × 10
H
B4
Initial value
0
Figure 2.3-9 Configuration of Interrupt Level Mask Register (ILM)
Initial value
2
MC-16LX general-purpose register and
).
H
to 1F .
H H
to 00037F
H
B0
B3 B2
B1
0 0 0
0
ILM0
ILM1
ILM2
0
0 0
CHAPTER 2 CPU
. However, it cannot be used as a
H
37