Fujitsu F2MC-16LX Hardware Manual page 377

[bit 10] OVIE (timer overflow interrupt request permission)
Measurement termination interrupt request during the pulse width measurement is controlled as shown
in the table below:
OVIE
0 Overflow interrupt request output disabled (interrupt is not generated even if OVIR is set). [Initial value]
1 Overflow interrupt request output enabled (interrupt is generated when OVIR is set).
• Initialized to "0" at reset.
• Reading and writing are allowed.
[bit 9] ERR (error flag)
This flag indicates the next measurement termination before reading the measured result in the PWCR
in the pulse width measurement in the continuous measurement mode. In this case, the PWCR value is
updated with the new measurement result and the previous measurement result is lost. The
measurement is continued regardless of the bit value.
ERR
Set factor Set when measurement results that are not read yet are erased due to the following results:
Clear factor Because PWCR (measurement result) is read, it is clear.
• Initialized to "0" at reset.
• Only reading is allowed. Write operations have no effect.
[bit 8] Reserved bit
It is Reserved bit. Be sure to write "0".
[bit 7, bit 6] CKS1 and CKS0 (clock selection)
Internal count clock can be selected from three types shown in Table 15.2-3.
Table 15.2-3 Count Clock of 16 Bit Up Count Timer
CKS1 CKS0
Clock of machine clock divided by 4 (0.17 µs for 24 MHz machine clock) [Initial value]
0 0
Clock of machine clock divided by 16 (0.67 µs for 24 MHz machine clock)
0 1
Clock of machine clock divided by 32 (1.337 µs for 24 MHz machine clock)
1 0
1 1 Setting disabled (Undefined)
• Initialized to 00
• Read and write are enabled. However, setting "11B" is a interdiction.
Note:
Rewriting after the startup is an interdiction. Always perform the write operation before start or after
stop.
Operation mode
Operation mode
Operation mode
at reset.
B
CHAPTER 15 PWC TIMER
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