Fujitsu F2MC-16LX Hardware Manual page 260

CHAPTER 12 16-BIT I/O TIMER
[bit 12 to bit 10] MSI2,MSI1,MSI0 (Interrupt mask selection bit)
Bit to set the number of times the compare clear interrupt be masked. It consists of a 3-bit reload
counter and the count value is reloaded every time the counter value is "000
writing into the MSI2, MSI1, and MSI0 registers, the count value is also loaded. The number of masks
is the number of settings. (Example: Set "010
setting "000
[bit 9] ICLR (Compare clear interrupt flag bit)
It is the interrupt request flag of compare clear. When the compare clear register value matches with the
16-bit free-run timer value by compare operation, this bit is set to "1". When the interrupt request enable
bit (ICRE of bit 8) is set, an interrupt is generated. The ICLR bit is cleared by writing "0". Writing "1"
does not have the meaning. By the read-modify-write instruction, this bit is always read "1".
0
1
[bit 8] ICRE (Compare clear interrupt request enable bit)
It is the interrupt enable bits of compare clear. When the bit is "1" and the interrupt flag (ICLR of bit 9)
is set to "1", an interrupt is generated.
0
1
[bit 7] IVF (Time overflow generation flag bit)
It is the interrupt request flag of 16-bit free-run timer.
If the 16-bit free-run timer overflows, or the counter is cleared when it matches the compare clear
register through compare operation as a result the mode setting, the IVF bit is set to "1". When the
interrupt request enable bit (IVFE of bit 5) is set, an interrupt is generated. Writing "0" into it clears it.
Writing "1" does not have the meaning. The read-modify-write instructions always read "1" from this
bit.
0
1
[bit 6] IVFE (Time overflow interrupt enable bit)
It is Interrupt enable bit of 16-bit free-run timer. When the bit is "1" and the write flag (IVF of bit 5) is
set to "1", an interrupt is generated.
0
1
244
" cannot mask interrupt causes.
B
No Interrupt request
Interrupt request
Interrupt disabled
Interruption permission
No Interrupt request [Initial value]
Interrupt request
Interrupt disabled
Interruption permission
" if masked twice, interrupted at the third time) However,
B
". In addition, when
B
[Initial value]
[Initial value]
[Initial value]