Fujitsu F2MC-16LX Hardware Manual page 138

CHAPTER 4 RESET
Correspondence of Reset Factor Bit and Reset Factor
Figure 4.5-2 shows the configuration of the reset cause bits of the watchdog timer control register (WDTC).
Contents of reset cause bits and associated reset causes are shown in the Table 4.5-1.
For details, see the "10.2 Watchdog Timer Control Register (WDTC)" section.
Figure 4.5-2 Configuration of Reset Factor Bits (Watchdog Timer Control Register)
Watchdog Timer Control Register (WDTC)
Bit
0000A8
H
Table 4.5-1 Correspondence of Reset Factor Bit and Reset Factor
Reset Factor
Generating power-on reset
Generating watchdog timer overflow
Generating External reset request from RST terminal
Generation of software reset request
* : Previous state held
X: Indeterminate
Notes on Reset Factor Bit
At two or more reset factors
If more than one reset cause is generated, the corresponding each reset cause bits of the WDTC register will
be set to "1". For example, if an external reset request via the RST pin and an overflow are generated
simultaneously, ERST and WRST of reset cause bits are set to "1".
At power on reset
When a power on reset is generated, the PONR of reset cause bit is set to "1" and all the other reset cause
bits are made undefined. For this reason, the software must be designed so that all the reset cause bits other
than PONR will be ignored if PONR is "1".
Clearing of reset factor bit
Each of the reset cause bits is cleared only when the values are read from the WDTC register. Once a reset
cause is generated, the bit corresponding to it is not cleared even when the reset is generated (a setting of
"1" is retained).
Note:
If power is turned on when a power on reset has not been generated, the WDTC register values may
be unprotected.
122
15 - 8 7 6
(TBTC)
PONR WRST
Reserved
X X
R -
R: Read only W: Write only X: Indeterminate
5 4 3 2
ERST SRST WTE
X X X 1
R R R W
PONR WRST
1 X
* 1
* *
* *
1 0
WT1 WT0
1 1
Initial value
W W R/W
ERST SRST
X X
* *
1 *
* 1