CHAPTER 15 I
Bus Control Register (IBCR)
All bits except for the BER and BEIE bits are cleared when the I
0 in ICCR).
■ Bus Control Register (IBCR)
The configuration of the bus control register (IBCR) is shown below.
Address : 000094
[Bit 15] BER (Bus ERror)
This bit is the bus error interrupt request flag bit. For a read by a read modify instruction, "1" is always
If this bit is set, the EN bit of the CCR register is cleared, the I
halted. All bits of the IBSR and IBCR registers except BER and BEIE are cleared. Clear this bit before the
C interface is enabled (EN = 1) again.
[Conditions set this bit to "1"]
1. An illegal START or STOP condition at a specific location is detected (while an slave address or data is
2. The header section of a slave address is received during a 10-bit read access before 10-bit write access
with the first byte is performed.
3. A STOP condition is detected during transfer in master mode.
*: When the I
is received to prevent an incorrect bus error report from being issued.
Clears the bus error interrupt request flag.
Has no meaning.
Bus error not detected
Error condition detected
C interface is enabled during transfer, this detection flag is set after the first STOP condition
C interface is stopped, and data transfer is
C stops operating (EN =