Fujitsu F2MC-16LX Hardware Manual page 373

Block Diagram of PWC Timer
Figure 15.1-1 shows the PWC timer block diagram.
PWCR read
Overflow
Measurement
start edge
Measurement
end edge
Measurement end
intrrupt request
Overflow interrupt
request
15
Figure 15.1-1 Block Diagram of PWC Timer
Error
ERR
detection
PWCR
16
Reload
Data tranmit
16
16-bit Up count timer
Control circuit
Start edge End edge
Division ON/OFF
selection selection
Edge
detection
PIS0/PIS1
ERR
CKS0/CKS1
PWCSR
2
Clock
2
2
3
2
Timer
clear
CKS1/CKS0
Count enabled
Input
waveform
comparator
8-bit
divider
Ratio selection
DIVR
CHAPTER 15 PWC TIMER
Internal clock (Machine clock/4)
Clock divider
Divider clear
PWC
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