Start/Stop Timing Of Shift Operation And Timing Of I/O - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 20 EXTENDED I/O SERIAL INTERFACE
20.3.3

Start/stop Timing of Shift Operation and Timing of I/O

Start/stop timing of shift operation and timing of I/O is described.
Start/stop Timing of Shift Operation and Timing of I/O
• Start
STOP bit of Start SMCS is set to "0", while STRT bit to "1".
• Stop
One halt is triggered from the termination of transfer; the other from STOP=1.
- Halt from STOP=1: Halts staying with SIR=0, regardless of MODE bit.
- Halt from transfer termination: Halts with SIR=1, regardless of MODE bit.
Regardless of MODE bit when BUSY bit is in the state of serial transfer, it is set to "1", and when in HALT
or R/W WAIT state, it is set to "0". Please read this bit to confirm forwarding.
The following chart shows the operation for each mode and the timing of halt operation. D07 to D00 in
figure shows output data.
Internal shift clock mode (LSB first)
Figure 20.3-3 Start/stop Timing of Shift Operation (Internal Clock)
SCK
STRT
BUSY
SOT
External shift clock mode (LSB first)
Figure 20.3-4 Start/stop Timing of Shift Operation (External Clock)
SCK
STRT
BUSY
SOT
For instruction shift in external shift clock mode (LSB first)
In instruction shift, when "1" is written to the bit corresponding to SCK of PDR, "H" is output, and when
"0" is written, "L" is output (where external shift clock mode is selected, and SCOE=0).
472
(Transfer start)
MODE=0
D00
(Transfer start)
MODE=0
D00
"1" Output
(Transfer complete)
(Data hold)
D07
(Transfer complete)
D07 (Data hold)