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MB90335 Series
2
19.2.2
I
C Bus Control Register 0 (IBCR0)
The configuration and functions of I
2
■ I
C Bus Control Register 0 (IBCR0)
Figure 19.2-3 shows the bit configuration of bus control register 0(IBCR0).
Figure 19.2-3 Bit Configuration of I
ch.0:000071
R/W : Readable/writable
The function of each bit of the bus control registers 0 (IBCR0) is described as follows:
[bit15] BER: Bus ERror
It is Bus error Interrupt request flag. Functions in writing phase differ from those as follows.
(at writing)
0
1
(at reading)
0
1
If BER bit is set, EN bit of ICCR0 register is cleared, the I
transfer is terminated.
[bit14] BEIE: Bus Error Interrupt Enable
It is bus error Interrupt enable bit.
0
1
The interruption is generated if the BER bit is "1" when this bit is "1".
CM44-10137-6E
2
C bus control register 0 (IBCR0) are described.
bit
15
14
13
12
11
H
BER BEIE SCC MSS ACK GCAA INTE INT
R/W R/W R/W R/W R/W R/W R/W R/W
Clear bus error interrupt request flag.
No effect on operation
The bus error is not detected.
Illegal start and stop condition was detected during data transfer.
Bus error interrupt disabled
Bus error interrupt enabled
FUJITSU MICROELECTRONICS LIMITED
2
C Bus Control Register 0 (IBCR0)
IBCR0
10
9
8
2
I
C Bus status register 0
Initial value
Read/Write
2
C interface goes into a halted state, and data
2
CHAPTER 19 I
C INTERFACE
2
19.2 I
C Interface Register
00000000
B
437
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