Detect Address Setting Registers (Padr0, Padr1) - Fujitsu F2MC-16LX Hardware Manual

24.3.2

Detect Address Setting Registers (PADR0, PADR1)

The value of an address to be detected is set in the detect address setting registers.
When the address of the instruction processed by the program matches the address set
in the detect address setting registers, the next instruction is forcibly replaced by the
INT9 instruction, and the interrupt processing program is executed.
Detect Address Setting Registers (PADR0, PADR1)
Figure 24.3-3 Detect Address Setting Registers (PADR0, PADR1)
PADR0, PADR1: High
Address 1FF2
H
PADR0, PADR1: Middle
Address 1FF1
H
PADR0, PADR1: Low
Address 1FF0
R/W : Read/Write
X : Undefined
bit 7 bit 6 bit 5
D23
, 1FF5
H
R/W
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
D15
, 1FF4
H
R/W
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
D7
, 1FF3
H H
R/W
CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION
bit 4 bit 3 bit 2 bit 1 bit 0
D22 D21 D20 D19
R/W R/W R/W R/W
D14 D13 D12 D11 D10
R/W R/W R/W R/W R/W
D6 D5 D4 D3
R/W R/W R/W R/W
Reset value
D18 D17 D16
XXXXXXXX
R/W R/W R/W
Reset value
D9 D8
XXXXXXXX
R/W R/W
Reset value
D2 D1 D0
XXXXXXXX
R/W R/W R/W
B
B
B
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