Input Capture - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 12 16-BIT I/O TIMER
12.2.3

Input Capture

This module has a function that detects a rising edge, falling edge, or both edges of
externally input signal and holds a value of the 16-bit free-run timer in a register at the
time of detection. It can also generate an interrupt when detecting an edge.
Input Capture
The input capture consist of input capture and control registers. Each input capture has its corresponding
external input pin.
• The valid edge of the external input can be selected from three types: Rising edge/falling edge/both
edges.
• It can generate an interrupt when it detects the valid edge of the external input.
Block Diagram of Input Capture
Figure 12.2-13 shows the input capture block diagram.
252
Figure 12.2-13 Block Diagram of Input Capture
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
Input capture data register 0
Input capture data register 1
16-bit timer counter value (T15 to T00)
Input capture data register 2
Input capture data register 3
ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20
Interrupt #25
IN0
Edge detection
IN1
Edge detection
Edge detection IN2
IN3
Edge detection
Interrupt #27