Fujitsu F2MC-16LX Hardware Manual page 225

Counter clear circuit
This circuit clears the counter by writing "0" to timebase timer initialization bit (TBR) of timebase timer
control register (TBTC), power-on reset, transition to the stop mode, switching to PLL clock mode from the
main clock mode or sub clock, or switching to the main clock mode from sub clock.
Interval timer selector
This selects the output of the timebase timer counter from one of four types. The overflow of selected bit
will be the interrupt cause.
Timebase timer control register (TBTC)
Interval time selection, counter clearance, and interrupt request control and status check are executed.
CHAPTER 9 TIMEBASE TIMER
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