Host Token Endpoint Register (Htoken) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 14 USB Mini-HOST
14.4.10

Host Token Endpoint Register (HTOKEN)

The host token endpoint register (HTOKEN) is a register that sets a toggle, endpoint,
and token.
Host Token Endpoint Register (HTOKEN)
Figure 14.4-10 Bit Configuration of Host Token Endpoint Register (HTOKEN)
Host token end point register
Address: 0000CE
H
→
Read/Write
→
Initial value
Reset On/Off at UDCC RST bit →
[bit 7] TGGL: Toggle
This bit sets toggle data. At transmission, the toggle data is sent according to the bit. At reception, the
received toggle data is compared to the toggle data which the bit shows and use at the error detection.
The bit is updated after the RST bit of the UDC control register (UDCC) is set to "0" and the TKNEN
bit to (0, 0, 0).
TGGL
0
1
[bit 6 to bit 4] TKNEN: Token permission
These bits send a token corresponding to the setting. After the operation is completed (bit6, bit5, bit4) =
(0, 0, 0), the CMPIRQ bit of the host interrupt register (HIRQ) is set to "1". At that time, if the CMPIRE
bit of the host control register 0 (HCNT0) is "1", an interrupt generates.
The TGGL and ENDPT bits are ignored during the SOF token. To write to the TKNEN bits, you must
set the RST bit in the UDC control register (UDCC) to "0" and turn the mode to host mode. In addition,
if you issue a token again because an interrupt due to a token is generated, you must wait three cycles or
longer in terms of USB transfer clock (12 MHz for Full Speed and 1.5 MHz for Low Speed) before
writing to the TKNEN bits. Note that writing to the TKNEN bits will not run a token in disconnection
status (HSTATE CSTAT= "0").
334
7 6 5
TGGL TKNEN
(R/W) (R/W)
(0) (000 )
B
( ) ( )
4 3 2
ENDPT
(R/W)
(0000
(
Operation Mode
Data 0
Data 1
←
1 0
bit number
HTOKEN
)
B
)