Operation Of 16-Bit Free-Run Timer - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 12 16-BIT I/O TIMER
12.3.1

Operation of 16-bit Free-run Timer

The operation and timing of the 16-bit free-run timer are described.
Operation of 16-bit Free-run Timer
The 16-bit free-run timer starts counting at the counter value of "0000
This counter value is a reference time for the 16-bit output compare and 16-bit input capture.
The count value is cleared by the following condition.
• When an overflow occurs
• When there is a comparing match with the value of output compare 0 (setting mode is required).
• When "1" is written into the CLR bit in the TCCS register while it is operating.
• When you write "0000
• At a reset
An interrupt is raised when an overflow occurs, or there is a comparing match with compare register 0 and
the counter value of 16-bit free-run timer (the compare-match interrupt requires mode setting).
Figure 12.3-1 shows the timing chart for clearing the counter due to overflow, and Figure 12.3-2 shows the
timing chart for clearing the counter due to compare-match operation.
Counter value
FFFF
BFFF
7FFF
3FFF
0000
Reset
Interrupt
256
" in the TCDC register while operating.
H
Figure 12.3-1 Timing Chart of Counter Clear by Overflow
H
H
H
H
H
" when a reset has been released.
H
Time