STMicroelectronics STM32F405 Reference Manual page 508

LCD-TFT Controller (LTDC)
16.7.25 LTDC Layerx CLUT Write Register (LTDC_LxCLUTWR)
(where x=1..2)
This register defines the CLUT address and the RGB value.
Address offset: 0xC4 + 0x80 x (Layerx -1), Layerx = 1 or 2
Reset value: 0x0000 0000
31 30 29 28
CLUTADD[7:0]
w w w w
15 14 13 12
GREEN[7:0]
w w w w
Bits 31:24 CLUTADD[7:0]: CLUT Address
Bits 23:16 RED[7:0]: Red value
Bits 15:8 GREEN[7:0]: Green value
Bits 7:0 BLUE[7:0]: Blue value
Note: The CLUT write register should only be configured during blanking period or if the layer is
disabled. The CLUT can be enabled or disabled in the LTDC_LxCR register.
The CLUT is only meaningful for L8, AL44 and AL88 pixel format.
508/1731
27 26 25
w w w
11 10 9
w w w
These bits configure the CLUT address (color position within the CLUT) of each RGB
value
These bits configure the red value
These bits configure the green value
These bits configure the blue value
DocID018909 Rev 11
24 23 22 21
w w w w
8 7 6 5
w w w w
20 19 18 17
RED[7:0]
w w w w
4 3 2 1
BLUE[7:0]
w w w w
RM0090
16
w
0
w