STMicroelectronics STM32F405 Reference Manual page 268

Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)
Addr. Register
offset name
RCC_
0x40
APB1ENR
RCC_
0x44
APB2ENR
0x48 Reserved
0x4C Reserved
RCC_AHB1LP
0x50
ENR
RCC_AHB2LP
0x54
ENR
RCC_AHB3LP
0x58
ENR
0x5C Reserved
RCC_APB1LP
0x60
ENR
RCC_APB2LP
0x64
ENR
0x68 Reserved
0x6C Reserved
0x70 RCC_BDCR
0x74 RCC_CSR
0x78 Reserved
0x7C Reserved
0x80 RCC_SSCGR
RCC_PLLI2SC
0x84 PLLI2SRx
FGR
Refer to
268/1731
Table 34. RCC register map and reset values (continued)
Reserved
Reserved
Reserved
Section 2.3: Memory map
DocID018909 Rev 11
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
INCSTEP
Reserved
for the register boundary addresses.
Reserved Reserved
Reserved
MODPER
PLLI2SNx
RM0090
Reserved