STMicroelectronics STM32F405 Reference Manual page 146

Power controller (PWR)
Bits 7:5 PLS[2:0]: PVD level selection
These bits are written by software to select the voltage threshold detected by the Power
Voltage Detector
Note: Refer to the electrical characteristics of the datasheet for more details.
Bit 4 PVDE: Power voltage detector enable
This bit is set and cleared by software.
Bit 3 CSBF: Clear standby flag
This bit is always read as 0.
Bit 2 CWUF: Clear wakeup flag
This bit is always read as 0.
Bit 1 PDDS: Power-down deepsleep
This bit is set and cleared by software. It works together with the LPDS bit.
Bit 0 LPDS: Low-power deepsleep
This bit is set and cleared by software. It works together with the PDDS bit.
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000: 2.0 V
001: 2.1 V
010: 2.3 V
011: 2.5 V
100: 2.6 V
101: 2.7 V
110: 2.8 V
111: 2.9 V
0: PVD disabled
1: PVD enabled
0: No effect
1: Clear the SBF Standby Flag (write).
0: No effect
1: Clear the WUF Wakeup Flag after 2 System clock cycles
0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the
LPDS bit.
1: Enter Standby mode when the CPU enters deepsleep.
0:Main voltage regulator ON during Stop mode
1: Low-power voltage regulator ON during Stop mode
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