STMicroelectronics STM32F405 Reference Manual page 109

RM0090
Bits 7:5 USER: User option bytes
These bits contain the value of the user option byte after reset. They can be written to program
a new user option byte value into Flash memory.
Note: When changing the WDG mode from hardware to software or from software to
Bit 4 BFB2: Dual-bank Boot option byte
Note: For STM32F42xx and STM32F43xx 1 MB part numbers, this option bit is reserved and
Bits 3:2 BOR_LEV: BOR reset Level
These bits contain the supply level threshold that activates/releases the reset. They can be
written to program a new BOR level. By default, BOR is off. When the supply voltage (V
drops below the selected BOR level, a device reset is generated.
Note: For full details on BOR characteristics, refer to the "Electrical characteristics" section of
Bit 1 OPTSTRT: Option start
This bit triggers a user option operation when set. It is set only by software and cleared when
the BSY bit is cleared.
Bit 0 OPTLOCK: Option lock
Write to 1 only. When this bit is set, it indicates that the FLASH_OPTCR register is locked. This
bit is cleared by hardware after detecting the unlock sequence.
In the event of an unsuccessful unlock operation, this bit remains set until the next reset.
Bit 7: nRST_STDBY
Bit 6: nRST_STOP
Bit 5: WDG_SW
hardware, a system reset is required to make the change effective.
0: Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from
system memory depending on boot pin state (default)
1: Dual-bank boot enabled. Boot is always performed from system memory.
must be kept cleared.
00: BOR Level 3 (VBOR3), brownout threshold level 3
01: BOR Level 2 (VBOR2), brownout threshold level 2
10: BOR Level 1 (VBOR1), brownout threshold level 1
11: BOR off, POR/PDR reset threshold level is applied
the product datasheet.
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Embedded Flash memory interface
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