STMicroelectronics STM32F405 Reference Manual page 61

RM0090
In the STM32F42xx and STM32F43xx devices, the main system consists of 32-bit multilayer
AHB bus matrix that interconnects:
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Ten masters:
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Eight slaves:
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The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously. The 64-
Kbyte CCM (core coupled memory) data RAM is not part of the bus matrix and can be
accessed only through the CPU. This architecture is shown in
®
Cortex -M4 with FPU core I-bus, D-bus and S-bus
DMA1 memory bus
DMA2 memory bus
DMA2 peripheral bus
Ethernet DMA bus
USB OTG HS DMA bus
LCD Controller DMA-bus
DMA2D (Chrom-Art Accelerator™) memory bus
Internal Flash memory ICode bus
Internal Flash memory DCode bus
Main internal SRAM1 (112 KB)
Auxiliary internal SRAM2 (16 KB)
Auxiliary internal SRAM3 (64 KB)
AHB1peripherals including AHB to APB bridges and APB peripherals
AHB2 peripherals
FMC
DocID018909 Rev 11
Memory and bus architecture
Figure 2.
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