STMicroelectronics STM32F405 Reference Manual page 107

RM0090
Bits 31:28 Reserved, must be kept cleared.
Bits 27:16 nWRP[11:0]: Not write protect
These bits contain the value of the write-protection option bytes after reset. They can be
written to program a new write protect value into Flash memory.
Bits 15:8 RDP[7:0]: Read protect
These bits contain the value of the read-protection option level after reset. They can be written
to program a new read protection value into Flash memory.
Bits 7:5 USER[2:0]: User option bytes
These bits contain the value of the user option byte after reset. They can be written to program
a new user option byte value into Flash memory.
Note: When changing the WDG mode from hardware to software or from software to
Bit 4 Reserved, must be kept cleared. Always read as "0".
Bits 3:2 BOR_LEV[1:0]: BOR reset Level
These bits contain the supply level threshold that activates/releases the reset. They can be
written to program a new BOR level. By default, BOR is off. When the supply voltage (V
drops below the selected BOR level, a device reset is generated.
Note: For full details about BOR characteristics, refer to the "Electrical characteristics" section
Bit 1 OPTSTRT: Option start
This bit triggers a user option operation when set. It is set only by software and cleared when
the BSY bit is cleared.
Bit 0 OPTLOCK: Option lock
Write to 1 only. When this bit is set, it indicates that the FLASH_OPTCR register is locked. This
bit is cleared by hardware after detecting the unlock sequence.
0: Write protection active on selected sector
1: Write protection inactive on selected sector
0xAA: Level 0, read protection not active
0xCC: Level 2, chip read protection active
Others: Level 1, read protection of memories active
Bit 7: nRST_STDBY
Bit 6: nRST_STOP
Bit 5: WDG_SW
hardware, a system reset is required to make the change effective.
00: BOR Level 3 (VBOR3), brownout threshold level 3
01: BOR Level 2 (VBOR2), brownout threshold level 2
10: BOR Level 1 (VBOR1), brownout threshold level 1
11: BOR off, POR/PDR reset threshold level is applied
in the device datasheet.
In the event of an unsuccessful unlock operation, this bit remains set until the next reset.
DocID018909 Rev 11
Embedded Flash memory interface
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