STMicroelectronics STM32F405 Reference Manual page 503

RM0090
16.7.18 LTDC Layerx Pixel Format Configuration Register (LTDC_LxPFCR)
(where x=1..2)
This register defines the pixel format which is used for the stored data in the frame buffer of
a layer. The pixel data is read from the frame buffer and then transformed to the internal
format 8888 (ARGB).
Address offset: 0x94 + 0x80 x (Layerx -1), Layerx = 1 or 2
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Bits 31:3 Reserved, must be kept at reset value
Bits 2:0 PF[2:0]: Pixel Format
16.7.19 LTDC Layerx Constant Alpha Configuration Register (LTDC_LxCACR)
(where x=1..2)
This register defines the constant alpha value (divided by 255 by Hardware), which is used
in the alpha blending. Refer to LTDC_LxBFCR register.
Address offset: 0x98 + 0x80 x (Layerx -1), Layerx = 1 or 2
Reset value: (Layerx -1) 0x0000 00FF
31 30 29 28
15 14 13 12
27 26 25
11 10 9
Reserved
These bits configures the Pixel format
000: ARGB8888
001: RGB888
010: RGB565
011: ARGB1555
100: ARGB4444
101: L8 (8-Bit Luminance)
110: AL44 (4-Bit Alpha, 4-Bit Luminance)
111: AL88 (8-Bit Alpha, 8-Bit Luminance)
27 26 25
11 10 9
Reserved
DocID018909 Rev 11
24 23 22 21
Reserved
8 7 6 5
24 23 22 21
Reserved
8 7 6 5
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LCD-TFT Controller (LTDC)
20 19 18 17
4 3 2 1
PF[2:0]
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20 19 18 17
4 3 2 1
CONSTA[7:0]
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0
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16
0
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