Analog-to-digital converter (ADC)
31
30
29
28
15
14
13
12
DMA[1:0]
DDS
Res.
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 TSVREFE: Temperature sensor and V
Note: On STM32F42x and STM32F43x devices, VBATE must be disabled when TSVREFE is
Bit 22 VBATE: V
Bits 21:18 Reserved, must be kept at reset value.
Bits 17:16 ADCPRE: ADC prescaler
Note: 00: PCLK2 divided by 2
Bits 15:14 DMA: Direct memory access mode for multi ADC mode
Bit 13 DDS: DMA disable selection (for multi-ADC mode)
Bit 12 Reserved, must be kept at reset value.
430/1731
27
26
25
Reserved
11
10
9
DELAY[3:0]
rw
rw
rw
This bit is set and cleared by software to enable/disable the temperature sensor and the
V
channel.
REFINT
0: Temperature sensor and V
1: Temperature sensor and V
set. If both bits are set, only the VBAT conversion is performed.
enable
BAT
This bit is set and cleared by software to enable/disable the V
0: V
channel disabled
BAT
1: V
channel enabled
BAT
Set and cleared by software to select the frequency of the clock to the ADC. The clock is
common for all the ADCs.
01: PCLK2 divided by 4
10: PCLK2 divided by 6
11: PCLK2 divided by 8
This bit-field is set and cleared by software. Refer to the DMA controller section for more
details.
00: DMA mode disabled
01: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)
10: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
11: DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2)
This bit is set and cleared by software.
0: No new DMA request is issued after the last transfer (as configured in the DMA
controller). DMA bits are not cleared by hardware, however they must have been cleared
and set to the wanted mode by software before new DMA requests can be generated.
1: DMA requests are issued as long as data are converted and DMA = 01, 10 or 11.
DocID018909 Rev 11
24
23
22
21
TSVREFE VBATE
rw
rw
8
7
6
Reserved
rw
enable
REFINT
channel disabled
REFINT
channel enabled
REFINT
20
19
18
Reserved
5
4
3
2
MULTI[4:0]
rw
rw
rw
channel.
BAT
RM0090
17
16
ADCPRE
rw
rw
1
0
rw
rw
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