STMicroelectronics STM32F405 Reference Manual page 190

Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
Bit 22 DMA2LPEN: DMA2 clock enable during Sleep mode
Bit 21 DMA1LPEN: DMA1 clock enable during Sleep mode
Bit 20 Reserved, must be kept at reset value.
Bit 19 SRAM3LPEN: SRAM3 interface clock enable during Sleep mode
Bit 18 BKPSRAMLPEN: Backup SRAM interface clock enable during Sleep mode
Bit 17 SRAM2LPEN: SRAM2 interface clock enable during Sleep mode
Bit 16 SRAM1LPEN: SRAM1 interface clock enable during Sleep mode
Bit 15 FLITFLPEN: Flash interface clock enable during Sleep mode
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 CRCLPEN: CRC clock enable during Sleep mode
Bit 11 Reserved, must be kept at reset value.
Bit 10 GPIOKLPEN: IO port K clock enable during Sleep mode
Bit 9 GPIOJLPEN: IO port J clock enable during Sleep mode
190/1731
This bit is set and cleared by software.
0: DMA2 clock disabled during Sleep mode
1: DMA2 clock enabled during Sleep mode
This bit is set and cleared by software.
0: DMA1 clock disabled during Sleep mode
1: DMA1 clock enabled during Sleep mode
This bit is set and cleared by software.
0: SRAM3 interface clock disabled during Sleep mode
1: SRAM3 interface clock enabled during Sleep mode
This bit is set and cleared by software.
0: Backup SRAM interface clock disabled during Sleep mode
1: Backup SRAM interface clock enabled during Sleep mode
This bit is set and cleared by software.
0: SRAM2 interface clock disabled during Sleep mode
1: SRAM2 interface clock enabled during Sleep mode
This bit is set and cleared by software.
0: SRAM1 interface clock disabled during Sleep mode
1: SRAM1 interface clock enabled during Sleep mode
This bit is set and cleared by software.
0: Flash interface clock disabled during Sleep mode
1: Flash interface clock enabled during Sleep mode
This bit is set and cleared by software.
0: CRC clock disabled during Sleep mode
1: CRC clock enabled during Sleep mode
This bit is set and cleared by software.
0: IO port K clock disabled during Sleep mode
1: IO port K clock enabled during Sleep mode
This bit is set and cleared by software.
0: IO port J clock disabled during Sleep mode
1: IO port J clock enabled during Sleep mode
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