Table of Contents
Advertisement
rfi
BIT
0
1
2
FIELD
19
BIT
16
17
18
FIELD
00000
Definition
Operation
Description
MOTOROLA
3
4
5
6
7
00000
19
20
21
22
23
Return from Interrupt
MSR[16–23, 25–27, 30–31] ← SRR1[16–23, 25–27, 30–31]
NIA ←iea SRR0[0–29] || 0b00
Bits SRR1[0,5-9,16-31] are placed into the corresponding bits of
the MSR. If the new MSR value does not enable any pending
exceptions, then the next instruction is fetched, under control of
the new MSR value, from the address SRR0[0–29] || 0b00. If the
new MSR value enables one or more pending exceptions, the
exception associated with the highest priority pending exception
is generated; in this case the value placed into SRR0 by the
exception processing mechanism is the address of the
instruction that would have been executed next had the
exception not occurred. Note that an implementation may define
addtional MSR bits, and in this case, may also cause them to be
saved to SRR1 from MSR on an exception and restored to MSR
from SRR1 on an rfi. This is a supervisor-level, context
synchronizing instruction.
Other registers altered:
MSR
POWERPC ARCHITECTURE
LEVEL
OEA
MPC823e REFERENCE MANUAL
MPC823e Instruction Set—rfi
8
9
10
11
12
00000
24
25
26
27
28
50
SUPERVISOR
OPTIONAL
LEVEL
√
13
14
15
29
30
31
0
FORM
XL
B-115
Advertisement
Table of Contents
