Using Rx Clock Correction; Enabling Clock Correction; Setting Rx Elastic Buffer Limits; Setting Clock Correction Sequences - Xilinx Virtex-6 FPGA User Manual

Using RX Clock Correction

The user must follow the steps described in this section to use the receiver clock correction.

Enabling Clock Correction

Each GTX transceiver includes a clock correction circuit that performs clock correction by
controlling the pointers of the RX elastic buffer. To use clock correction, RX_BUFFER_USE
is set to TRUE to turn on the RX elastic buffer, and CLK_CORRECT_USE is set to TRUE to
turn on the clock correction circuit.
Clock correction is triggered when the RX elastic buffer latency is too high or too low, and
the clock correction circuit detects a match sequence. To use clock correction, the clock
correction circuit must be configured to set the following items:
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Setting RX Elastic Buffer Limits

The RX elastic buffer limits are set using CLK_COR_MIN_LAT (minimum latency) and
CLK_COR_MAX_LAT (maximum latency). When the number of bytes in the RX elastic
buffer drops below CLK_COR_MIN_LAT, the clock correction circuit writes an additional
CLK_COR_ADJ_LEN bytes from the first clock correction sequence it matches to prevent
the buffer from underflowing. Similarly, when the number of bytes in the RX elastic buffer
exceeds CLK_COR_MAX_LAT, the clock correction circuit deletes CLK_COR_ADJ_LEN
bytes from the first clock correction sequence it matches, starting with the first byte of the
sequence.

Setting Clock Correction Sequences

The clock correction sequences are programmed using the CLK_COR_SEQ_1_* attributes
and CLK_COR_ADJ_LEN. Each CLK_COR_SEQ_1_* attribute corresponds to one
subsequence in clock correction sequence 1. CLK_COR_ADJ_LEN is used to set the
number of subsequences to be matched. If the 20-bit internal datapath is used, the clock
correction circuit matches all 10 bits of each subsequence. If the 16-bit internal datapath is
used, only the right-most eight bits of each subsequence are used.
A second, alternate clock correction sequence can be activated by setting
CLK_COR_SEQ_2_USE to TRUE. The first and second sequences share length settings, but
use different subsequence values for matching. Set the CLK_COR_SEQ_2_* attributes to
define the subsequence values for the second sequence.
When using 8B/10B decoding (RXDEC8B10BUSE is High), RX_DECODE_SEQ_MATCH
is set to TRUE to search the output of the 8B/10B decoder for sequence matches instead of
non-decoded data. This allows the circuit to look for 8-bit values with either positive or
negative disparity, and to distinguish K characters from regular characters (see
Encoder, page 143
to set a clock correction sequence byte when RX_DECODE_SEQ_MATCH is TRUE.
When RX_DECODE_SEQ_MATCH is FALSE, the sequence must exactly match non-
encoded incoming data.
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
RX elastic buffer limits
Clock correction sequence
and RX 8B/10B Decoder, page 228
www.xilinx.com
RX Clock Correction
TX 8B/10B
for details). Figure 4-36 shows how
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