Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2196

3. Disable the MAC transmitter and MAC receiver by clearing the EMAC_MACCFG.TE and
EMAC_MACCFG.RE bits.
4. Disable the receive DMA (if applicable), after ensuring that the data in the receive FIFO transfers to the system
memory by reading the
5. Make sure that both the transmit and receive FIFOs are empty.
6. To restart the operation, first start the DMA, and then enable the MAC transmitter and receiver.
Interrupts and Interrupt Service Routines
The following procedure describes specific steps for enabling interrupts and using their ISRs.
This procedure is typically performed with EMAC and DMA initialization and operations.
1. Receive interrupts are enabled for descriptors by default. Enable transmit interrupts for individual descriptors
by setting the IC bit (bit 30) in the TDES0 word of the transmit descriptor.
2. Enable the required bits in the DMA interrupt enable register (EMAC_DMA0_IEN.NIE) .
ADDITIONAL INFORMATION: Setting the EMAC_DMA0_IEN.NIE or EMAC_DMA0_IEN.AIE bits can
turn on the occurrence of all normal or abnormal interrupt conditions. Individual conditions can also be ena-
bled on using individual bits in the
3. Enable MMC overflow interrupts by setting appropriate bits in the
EMAC_MMC_TXIMSK
4. Enable PTP interrupts by setting the EMAC_IMSK.TS bit.
5. Once an EMAC interrupt is asserted and the SEC branches execution to the EMAC ISR, perform the follow-
ing software program sequence.
a. Read DMA status from the
b. Clear the interrupt source by writing 1 (W1C) to the bits that are set in the
c. Check for normal/abnormal/mmc/ptp interrupts by parsing the status bits read earlier, and call the appro-
priate service function.
ADDITIONAL INFORMATION: Normal interrupt assertions include the transmit and receive interrupt.
Abnormal interrupt assertions include the receive underflow.
6. The MMC handler functions use the following sequence.
a. Read the
EMAC_ISTAT
bits to determine if the interrupt is a transmit counter or receive counter-interrupt.
b. Read the
EMAC_MMC_RXINT
triggered the interrupt.
c. Read the respective MMC counter that caused the interrupt to clear it.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register.
EMAC_DBG
EMAC_DMA0_IEN
registers.
EMAC_DMA0_STAT
register and parse for the EMAC_ISTAT.MMCTX and EMAC_ISTAT.MMCRX
or
EMAC_MMC_TXINT
register.
EMAC_MMC_RXIMSK
register.
registers to determine which of the counters have
EMAC Programming Steps
and
register.
EMAC_DMA0_STAT
31–105