Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2191

EMAC Event Control
Controller (SEC) and Generic Interrupt Controller (GIC)
uct and how to configure them.
EMAC Interrupt Signals
Interrupts from the EMAC are triggered from the EMAC DMA layer or the EMAC CORE layer. Interrupts are
triggered from EMAC DMA when a particular status bit is set in the
line is asserted only when the corresponding bits are enabled in the DMA interrupt enable register. Similarly, inter-
rupts are triggered from the EMAC CORE when a particular MMC status bit, RGMII Link status bit, or PTP sta-
tus bit is set in the interrupt status register.
An interrupt line is asserted only when the corresponding bits are enabled in the MMC mask registers for MMC
counters or the interrupt mask register for PTP. DMA status register also reflects the MMC interrupt status. The
following lists show the two groups of interrupts in the DMA status register.
NIS – Normal Interrupt source summary:
• Transmit Interrupt
• Transmit Buffer Unavailable
• Receive Interrupt
• Early Receive Interrupt
AIS – Abnormal Interrupt source summary:
• Transmit Process Stopped
• Transmit Jabber Timeout
• Receive FIFO Overflow
• Transmit Underflow
• Receive Buffer Unavailable
• Receive Process Stopped
• Receive Watchdog Timeout
• Early Transmit Interrupt
• Fatal Bus Error
The EMAC generates an interrupt only once for simultaneous, multiple events. The driver must read the
register for the cause of the interrupt. It can generate a new interrupt once the driver has
EMAC_DMA0_STAT
cleared the appropriate bit in DMA status register.
For example, the controller generates a receive interrupt (EMAC_DMA0_STAT.RI bit) and the driver begins read-
ing the EMAC_DMA0_STAT
occurs. The driver clears the EMAC_DMA0_STAT.RI bit but the internal interrupt signal is not deasserted,
31–100
register. Next, a receive buffer unavailable interrupt (EMAC_DMA0_STAT.RU bit)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
chapter for details on how interrupts work in this prod-
EMAC_DMA0_STAT register. An interrupt