Configuration Of The Time-Base Timer - Fujitsu MB90460 Series Hardware Manual

CHAPTER 10 TIME-BASE TIMER
10.2

Configuration of the Time-base Timer

The time-base timer consists of the following four blocks:
• Time-base timer counter
• Counter clear circuit
• Interval timer selector
• Time-base timer control register (TBTC)
■ Block Diagram of the Time-base Timer
Figure 10.2-1 shows the block diagram of the time-base timer.
Time-base
timer counter
Divide-by
×
-two HCLK
Power-on reset
Stop mode start
CKSCR: MCS = 1 to 0(*1)
Time-base timer
interrupt signal
#36 (24 )(*2)
H
OF:Overflow
HCLK: Oscillation clock
*1 : Switching of the machine clock from the oscillation clock to the PLL clock
*2 : Interrupt number
●
Time-base timer counter
This 18-bit up counter uses the divide-by-two clock of the oscillation clock (HCLK) as the count clock.
●
Counter clear circuit
Used to clear the counter by writing "0" to the TBTC:TBR bit, by a power-on reset or by transition to stop
mode (LPMCR: STP = 1).
●
Interval timer selector
Selects one of four outputs of the time-base timer counter. An overflow of the selected bit becomes an
interrupt cause.
●
Time-base timer control register (TBTC)
Selects the interval, clears the counter, controls an interrupt request, and checks the status.
208
Figure 10.2-1 Block Diagram of the Time-base Timer
× ×
1 2 3 × 8
. . . . . .
2 2 2 2
Counter clear
Counter
clear circuit
TBOF clear
× × × ×
9 × 10 11 12 13 × 14
2 2 2 2 2 2
OF
OF
Interval
timer selector
— — —
TBIE TBOF
To watchdog timer
× × ×
15 × 16 17 18
2 2 2 2
OF
OF
OF
To the oscillation
setting time selector
in the clock control
section
TBOF set
TBR TBC1 TBC0
Time-base timer
interrpt register (TBTC)