Μpg Timer Registers - Fujitsu F2MC-16LX Hardware Manual
Mb90470 series 16-bit microcontroller
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Also See for F2MC-16LX:
- Hardware manual (706 pages) ,
- Application note (13 pages) ,
- Operation manual (10 pages)
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15.2 µ µ µ µ PG Timer Registers
This section describes the configurations of the registers used in the µ µ µ µ PG timer and
their functions.
I Configuration of µ µ µ µ PG timer registers
Figure 15.2-1 "Configuration of µPG timer registers" illustrates the configuration of the µPG
timer registers.
7
00008E
PEN0 PE1
H
(R/W) (R/W) ((R/W))(R/W) (R/W)
I PG control/status register (PGCSR)
The bit configuration of the PG control/status register (PGCSR) is shown below.
7
00008E
PEN0 PE1
H
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
The functions of the bits in the PG control/status register (PGCSR) are listed below.
[bit 7] PEN0 (operation enable)
This bit is used to enable µPG timer operation.
PEN0
0
1
•
This bit is initialized at reset.
[Bits 6, 5] PE1, PE0 (output enable)
These bits are used to control the pulse output external pin.
PE1
0
0
1
1
•
These bits are initialized to 00
Figure 15.2-1 Configuration of µ µ µ µ PG timer registers
6
5
4
PE0 PMT1 PMT0
6
5
4
3
PE0 PMT1 PMT0
(0)
(0)
(0)
(0)
Stop (retaining "L" level) (initial value)
PG operation allowed
PE0
0
General-purpose support pin (pulse output prohibited) (initial value)
1
MT00 pulse output pin only (output allowed)
0
MT01 pulse output pin only (output allowed)
1
MT00,MT01 pulse output pin (output allowed)
B
3
2
1
0
-
-
-
(-)
(-)
(-)
2
1
0
PG
-
-
-
-
(-)
(-)
(-)
Reading/writing
(-)
(-)
(-)
Initial value
Function
Operation control function
at reset.
CHAPTER 15 µ µ µ µ PG TIMER
UPG
Operation mode control register
Initial value 00000----
B
Operation mode control register
305
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