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CHAPTER 8 16-BIT RELOAD TIMER
8.3
16-bit Reload Timer Registers
This section describes the configuration and functions of reload timer registers.
■ Control Status Register (TMCSR:TMCSR0 to TMCSR2)
Control status register (TMCSR)
Address
TMCSR0: 00004E
TMCSR1: 000056
TMCSR2: 00005E
This register controls 16-bit timer operation modes and interrupts.
Rewrite bits other than UF, CNTE, and TRG only when CNTE = 0.
[bit12, bit11, bit10] CSL2, CSL1, CSL0 (Count source select)
These bits are count source select bits. Count sources can be selected from internal clocks and external
triggers. Selectable count sources are as follows.
CSL2
0
0
0
0
1
1
1
1
The count effective edges are set using the MOD1 and MOD0 bits when external triggers are specified for
count sources.
The minimum pulse width necessary for external triggers is 2×T (T: Machine clock cycle).
By using ch.1+ch.2 cascade connection, only ch.2 register can be set when CSL2, CSL1, CSL0="111
Setting is prohibited in ch.1.
154
15
14
13
–
–
–
H
–
–
–
H
(X)
(X)
(X)
H
7
6
5
MOD0
–
OUTL
R/W
R
R/W
(0)
(0)
(0)
CSL1
CSL0
Count source (φ: Machine clock)
0
0
Internal clock φ/2
0
1
Internal clock φ/2
1
0
Internal clock φ/2
1
1
External trigger
0
0
Setting prohibited
0
1
Internal clock φ/2
1
0
Internal clock φ/2
1
1
ch.1 timer output (only ch.2 is settable)
12
11
10
CSL2
CSL1
CSL0 MOD2 MOD1
R/W
R/W
R/W
R/W
(0)
(0)
(0)
4
3
2
RELD
INTE
UF
CNTE
R/W
R/W
R/W
R/W
(0)
(0)
(0)
1
(Initial value)
3
5
6
7
← Bit No.
9
8
← Read/Write
R/W
← Initial value
(0)
(0)
← Bit No.
1
0
TRG
← Read/Write
R/W
← Initial value
(0)
(0)
φ=32 MHz
62.5 ns
250 ns
1.0 µs
–
–
2.0 µs
4.0 µs
ch.1
φ=16 MHz
125 ns
0.5 µs
2.0 µs
–
–
4.0 µs
8.0 µs
ch.1
".
B
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