Renesas H8/38024 Hardware Manual page 361

Bit 2—Transmit End Interrupt Enable (TEIE)
Bit 2 selects enabling or disabling of the transmit end interrupt request (TEI) if there is no valid
transmit data in TDR when MSB data is to be sent.
Bit 2
TEIE Description
0 Transmit end interrupt request (TEI) disabled
Transmit end interrupt request (TEI) enabled *
1
Note: * TEI can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by
clearing bit TEIE to 0.
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0)
Bits 1 and 0 select the clock source and enabling or disabling of clock output from the SCK
The combination of CKE1 and CKE0 determines whether the SCK
a clock output pin, or a clock input pin.
The CKE0 bit setting is only valid in case of internal clock operation (CKE1 = 0) in asynchronous
mode. In synchronous mode, or when external clock operation is used (CKE1 = 1), bit CKE0
should be cleared to 0.
After setting bits CKE1 and CKE0, set the operating mode in the serial mode register (SMR).
For details on clock source selection, see table 10.9 in section 10.3.1, Overview.
Bit 1 Bit 0
CKE1 CKE0
0 0
0 1
1 0
1 1
Notes: 1. Initial value
2. A clock with the same frequency as the bit rate is output.
3. Input a clock with a frequency 16 times the bit rate.
Communication Mode
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
pin functions as an I/O port,
32
Description
Clock Source SCK
I/O port *
Internal clock
Serial clock output *
Internal clock
Clock output *
Internal clock
Reserved
Clock input *
External clock
External clock Serial clock input
Reserved
Reserved
Rev. 6.00, 08/04, page 331 of 628
(initial value)
pin.
32
Pin Function
32
1
1
2
3