Renesas H8/38024 Hardware Manual page 383

SCI3 operates as follows when transmitting data.
SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Serial data is transmitted from the TXD
When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data
from TDR to TSR, and when the stop bit has been sent, starts transmission of the next frame. If
bit TDRE is set to 1, bit TEND in SSR bit is set to 1the mark state, in which 1s are transmitted, is
established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this time, a TEI
request is made.
Figure 10.7 shows an example of the operation when transmitting in asynchronous mode.
Start
bit
Serial
1 0 D0
data
TDRE
TEND
LSI TXI request
operation
User
processing
Figure 10.7 Example of Operation when Transmitting in Asynchronous Mode
pin using the relevant data transfer format in table 10.11.
32
Transmit Parity
data bit
D1 D7 0/1
1 frame
TDRE TXI request
cleared to 0
Data written
to TDR
(8-bit data, parity, 1 stop bit)
Stop Start Transmit
bit bit data
1 0 D0 D1
1 frame
Rev. 6.00, 08/04, page 353 of 628
Parity Stop Mark
bit bit state
D7 0/1 1
TEI request
1