Renesas H8/38024 Hardware Manual page 12

Item
9.6.2 Register
Descriptions
9.7.2 Register
Configurations
9.7.3 Operation
Figure 9.22 Event
Counter Operation
Waveform
14.1 Overview
14.2.1 Low-Voltage
Detection Control
Register (LVDCR)
Table 14.3 LVDCR
Settings and Function
Register Selections
14.2.2 Low-Voltage
Detection Status
Register (LVDSR)
14.3.2 Low-Voltage
Detection Circuit
LVDR (Reset by Low
Voltage Detect) Circuit:
LVDI (Interrupt by Low
Voltage Detect) Circuit:
Rev. 6.00, 08/04, page xii of xxx
Page Revisions (See Manual for Details)
297 Timer Mode Register (TMW)
Bits 3 to 0—Clock Select (CKS3 to CKS0)
Bit table amended
Bit 3 Bit 2
CKS3 CKS2
0 X
309 Event Counter Control/Status Register (ECCSR)
Description amended
• Bit 7—Control Overflow H (OVH)
• Bit 6—Counter Overflow L (OVL)
316 Event Counter PWM Operation
Figure 9.22 amended
Ndr: Value of ECPWDRH and ECPWDRL Fixed low when Ndr
= H'FFFF
423 Note * added
Note: * The voltage maintained in standby mode is the same as
the RAM data retaining voltage (VRAM). See section 16.8.2,
DC Characteristics, for information on retaining voltage.
428 Note added
Note: Setting values marked with an asterisk (*) are invalid.
428 Note amended
Note: * These bits
432 Description amended
To operate the LVDR, set the LVDE bit in LVDCR to 1, wait for
150 µs (t
LVDON
detection power supply have stabilized, based on overflow of
LVDNT, etc., then set the LVDRE bit in LVDCR to 1.
433 Description amended
To operate the LVDI, set the LVDE bit in LVDCR to 1, wait for
150 µs (t
LVDON
detection power supply have stabilized, based on overflow of
LVDNT, etc., then set the LVDDE and LVDUE bits in LVDCR to
1.
Bit 1 Bit 0
CKS1 CKS0
X X
initialized by resets trigged by LVDR.
) until the reference voltage and the low-voltage-
) until the reference voltage and the low-voltage-
Description
Watchdog on-chip oscillator