Renesas H8/38024 Hardware Manual page 133

Clock Pulse Generator Control Register (OSCCR)
Bit 7
SUBSTP
Initial value 0
Read/Write R/W
OSCCR is an 8-bit read/write register that contains the flag indicating the selection of system
clock oscillator or on-chip oscillator, indicates the input level of the IRQAEC pin during resets,
and controls whether the subclock oscillator operates or not.
Bit 7—Subclock Oscillator Stop Control (SUBSTP)
Bit 7 controls whether the subclock oscillator operates or not. It can be set to 1 only in the active
mode (high-speed/medium-speed). Setting bit 7 to 1 in the subactive mode will cause the LSI to
stop operating.
Bit 7
SUBSTP Description
0 Subclock oscillator operates
1 Subclock oscillator stopped
Bit 6—Reserved
This bit is reserved. It is always read as 0 and cannot be written to.
Bits 5 to 3—Reserved
These bits are read/write enabled reserved bits.
Bit 2—IRQAEC Flag (IRQAECF)
This bit indicates the IRQAEC pin input level set during resets.
Bit 2
IRQAECF Description
0 IRQAEC pin set to GND during resets
1 IRQAEC pin set to V
6 5
— — —
0 0
R R/W R/W
during resets
CC
4 3 2
— IRQAECF OSCF
0 0 —
R/W R
Rev. 6.00, 08/04, page 103 of 628
1 0
—
— 0
R R/W
(initial value)