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Figure 9.22 and table 9.20 show examples of event counter PWM operation.
= T × (N
t
off
dr
= T × (N
t
cm
Note: N
and N
above must be set so that N
dr
cm
condition, do not set ECPWME in AEGSR to 1.
Table 9.20 Examples of Event Counter PWM Operation
Conditions: f
= 4 MHz, f
osc
ECPWDR value (N
Clock Source
Clock Source
Cycle (T) *
Selection
φ/2
1 µs
φ/4
2 µs
φ/8
4 µs
φ/16
8 µs
φ/32
16 µs
φ/64
32 µs
Note: * t
minimum width
off
Clock Input Enable/Disable Function Operation
The clock input to the event counter can be controlled by the IRQAEC pin when ECPWME in
AEGSR is 0, and by event counter PWM output IECPWM when ECPWME in AEGSR is 1. As
this function forcibly terminates the clock input by each signal, a maximum error of one count will
occur depending the IRQAEC or IECPWM timing.
Rev. 6.00, 08/04, page 316 of 628
+1)
t
on
+1)
cm
Figure 9.22 Event Counter Operation Waveform
= 2 MHz, high-speed active mode, ECPWCR value (N
φ
) = H'16E3
dr
ECPWCR
Value (N
cm
H'7A11
D'31249
T
:
Clock input enabled time
on
T
:
Clock input disabled time
off
T
: One conversion period
cm
T :
ECPWM input clock cycle
N
:
Value of ECPWDRH and ECPWDRL
dr
Fixed low when Ndr = H'FFFF
N
: Value of ECPWCRH and ECPWCRL
cm
< N
. If the settings do not satisfy this
dr
cm
ECPWDR
t
= T •
off
)
Value (N
)
(N
+ 1)
dr
dr
H'16E3
5.86 ms
D'5859
11.72 ms
23.44 ms
46.88 ms
93.76 ms
187.52 ms 1000.0 ms 812.48 ms
) = H'7A11,
cm
t
= T •
cm
(N
+ 1)
t
= t
cm
on
cm
31.25 ms
25.39 ms
62.5 ms
50.78 ms
125.0 ms
101.56 ms
250.0 ms
203.12 ms
500.0 ms
406.24 ms
– t
off
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