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FP-80A
Type
Symbol
TFP-80C FP-80B TLP-85V
Clock
OSC
10
1
pins
OSC
9
2
X
6
1
X
7
2
RES
System
12
control
TEST
11
IRQ
Interrupt
72
0
IRQ
pins
76
1
IRQ
5
3
IRQ
3
4
IRQAEC 60
WKP
to
20 to 13
7
WKP
0
Rev. 6.00, 08/04, page 20 of 628
Pin No.
Pad
No. *
12
F2
11
11
E3
10
8
D3
6
9
D2
7
14
F3
13
13
E2
12
74
C5
73
78
B3
77
7
D1
5
5
B2
3
62
C10
61
22 to 15 H1, J1,
21 to
H3, G1,
14
H2, G2,
F2, G3
Pad
Pad
1
No. *
2
No. *
3
I/O
12
10
Input
11
9
Output
7
6
Input
8
7
Output
14
12
Input
13
11
Input
74
72
Input
78
76
6
5
4
3
62
60
Input
22 to
20 to
Input
15
13
Name and Functions
These pins connect to a
crystal or ceramic
oscillator, or can be used
to input an external clock.
See section 4, Clock
Pulse Generators, for a
typical connection
diagram.
These pins connect to a
32.768-kHz or 38.4-kHz
crystal oscillator.
See section 4, Clock
Pulse Generators, for a
typical connection
diagram.
Reset: When this pin is
driven low, the chip is
reset
Test pin: This pin is
reserved and cannot be
used. It should be
connected to V
.
SS
IRQ interrupt request 0,
1, 3, and 4: These are
input pins for edge-
sensitive external
interrupts, with a selection
of rising or falling edge
Asynchronous event
counter event signal:
This is an interrupt input
pin for enabling
asynchronous event
input.
On the H8/38124 Group,
this must be fixed at V
CC
or GND because the
oscillator is selected by
the input level during
resets. Refer to section 4,
Clock Pulse Generators,
for information on the
selection method.
Wakeup interrupt
request 7 to 0: These are
input pins for rising or
falling-edge-sensitive
external interrupts.
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