Renesas H8/38024 Hardware Manual page 421

Bit 7—Clock Select (CKS)
Bit 7 sets the A/D conversion speed.
Bit 7
CKS Conversion Period
0 62/φ (initial value)
1 31/φ
Note: * For the H8/38024, H8/38024S, H8/38024F-ZTAT, and H8/38124 groups, operation is not
guaranteed if the conversion time is less than 7.8 µs. A conversion time of 7.8 µs or
greater should be selected.
Operation is not guaranteed if the conversion time is less than 12.4 µs. Set bit 7 for a
value of at least 12.4 µs.
Bit 6—External Trigger Select (TRGE)
Bit 6 enables or disables the start of A/D conversion by external trigger input.
Bit 6
TRGE Description
0 Disables start of A/D conversion by external trigger
1 Enables start of A/D conversion by rising or falling edge of external trigger at pin
ADTRG *
Note: * The external trigger (ADTRG) edge is selected by bit IEG4 of IEGR. See 1. IRQ edge
select register (IEGR) in section 3.3.2 for details.
Bits 5 and 4—Reserved
Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified.
Bits 3 to 0—Channel Select (CH3 to CH0)
Bits 3 to 0 select the analog input channel.
The channel selection should be made while bit ADSF is cleared to 0.
Conversion Time
φ φ φ φ = 1 MHz φ φ φ φ = 5 MHz
62 µs 12.4 µs
31 µs —*
Rev. 6.00, 08/04, page 391 of 628
φ φ φ φ = 8 MHz
7.8 µs
—*
(initial value)