Renesas H8/38024 Hardware Manual page 341

Bit 2—Count-up Enable L (CUEL)
Bit 2 enables event clock input to ECL. When 1 is written to this bit, event clock input is enabled
and increments the counter. When 0 is written to this bit, event clock input is disabled and the
ECL value is held.
Bit 2
CUEL Description
0 ECL event clock input is disabled
ECL value is held
1 ECL event clock input is enabled
Bit 1—Counter Reset Control H (CRCH)
Bit 1 controls resetting of ECH. When this bit is cleared to 0, ECH is reset. When 1 is written to
this bit, the counter reset is cleared and the ECH count-up function is enabled.
Bit 1
CRCH Description
0 ECH is reset
1 ECH reset is cleared and count-up function is enabled
Bit 0—Counter Reset Control L (CRCL)
Bit 0 controls resetting of ECL. When this bit is cleared to 0, ECL is reset. When 1 is written to
this bit, the counter reset is cleared and the ECL count-up function is enabled.
Bit 0
CRCL Description
0 ECL is reset
1 ECL reset is cleared and count-up function is enabled
Event Counter H (ECH)
Bit 7
ECH7
Initial Value 0
Read/Write
R
ECH is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL. The
external asynchronous event AEVH pin, φ/2, φ/4, φ/8, or the overflow signal from lower 8-bit
6 5
ECH6 ECH5
0 0
R R
4 3
ECH4 ECH3
0 0
R R
Rev. 6.00, 08/04, page 311 of 628
(initial value)
(initial value)
(initial value)
2 1
ECH2 ECH1 ECH0
0 0
R R
0
0
R