Renesas H8/38024 Hardware Manual page 223

Bit 2—Watchdog Timer Source Clock (WDCKS)
This bit selects the watchdog timer source clock. Note that stabilization times for the H8/38024,
H8/38024S, and H8/38024F-ZTAT Group and for the H8/38124 Group are different.
• H8/38024, H8/38024S, H8/38024F-ZTAT Group
Bit 2
WDCKS Description
Selects φ/8192
0
Selects φ
1
• H8/38124 Group
Bit 2
WDCKS Description
Selects clock based on timer mode register W (TMW) setting *
0
Selects φ
1
Note: * See section 9.6, Watchdog Timer, for details.
Bit 1—TMIG Noise Canceller Select (NCS)
This bit selects controls the noise cancellation circuit of the input capture input signal (TMIG).
Bit 1
NCS Description
0 No noise cancellation circuit
1 Noise cancellation circuit
/32
W
/32
W
(initial value)
(initial value)
(initial value)
Rev. 6.00, 08/04, page 193 of 628